Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening ...

A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) ...

In my August 2021 column, I introduced the composites building block approach as a step-by-step series of mechanical tests of increasing complexity, coupled with analyses performed at each step, that ...

If you can't pick up the schematic and know (at a moderately high level) what the design is supposed to do and how it is supposed to do it, then you have not really done your job as the designer. The ...