EDN

Internal test in FPGA design

http://www.xilinx.comAs the density of field-programmable-gate arrays (FPGAs) continues to increase, engineers are challenged to come up with ways to test and verify ...
Design-Reuse

Preservation of Circuit Structure and Timing during Fault Emulation in FPGA

This paper presents a technique that allows to preserve structure of a circuit according to a target technology during fault emulation in FPGA. The technique is not restricted to any target technology ...
Semiconductor Engineering

Adding NoCs To FPGA SoCs

FPGA SoCs straddle the line between flexibility and performance by combining elements of both FPGAs and ASICs. But as they find a home in more safety- and mission-critical markets, they also are ...
EDN

S2C Releases TAI Player Pro Software Version 3.1 with Multi-FPGA Internal Logic Analyzer

Version 3.1 has significantly made SoC prototyping on FPGA a much easier task than before San Jose, California – May 11, 2009 – S2C Inc., a leading total solution provider in facilitating systems to ...
Electronic Design

Choose The Optimal Clocking Solution For FPGA-Based Designs

This file type includes high resolution graphics and schematics when applicable. FGPAs are used in a large variety of applications, ranging from embedded computing to high-speed serial digital ...