Building Generative AI models depends heavily on how fast models can reach their data. Memory bandwidth, total capacity, and ...

The biggest challenge posed by AI training is in moving the massive datasets between the memory and processor.

SPHBM4 cuts pin counts dramatically while preserving hyperscale-class bandwidth performanceOrganic substrates reduce packaging costs and relax routing constraints in HBM designsSerialization shifts ...

Researchers propose low-latency topologies and processing-in-network as memory and interconnect bottlenecks threaten inference economic viability ...

The scaling of computational power within a single, packaged semiconductor component continues to rise following a Moore’s law type curve enabling new and more capable applications including machine ...

In October 2025, Samsung Electronics and SK Hynix struck a deal with OpenAI, which saw the three companies sign a letter of intent for the eventual supply of 900,000 DRAM wafers a month in order to ...

Micron Technology is thriving in the high bandwidth memory market, leading to a profit beat and strong forecast for the next quarter. The company’s HBM3e shipments are scaling up, with expectations of ...

Once a commoditised component, memory has become the most critical bottleneck in the AI era, with rising prices reshaping the ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence (Nasdaq: CDNS) today announced the tapeout of the industry’s first LPDDR6/5X memory IP system solution optimized to operate at 14.4Gbps, up to 50% faster ...

Micron Technology's HBM up-scaling is driving significant profit growth, with profits expected to surge 433% in 2025 and 60% in 2026. Despite disappointing 2Q25 sales guidance, Micron's robust demand ...