A cornerstone of effective STCO is the ability to conduct multi-domain analyses—for example, signal integrity, power integrity, thermal performance, and mechanical stress—at a very early stage in the ...

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly become a critical and essential technology that addresses the increasing complexity of ...

"With great power comes great responsibility," says Spider-Man's wise Uncle Ben. Who knew he was really talking about electronic design, FETs, source nets, and switching frequencies? Power MOSFETs are ...

Cupertino, Calif. How do you design a 10-million-gate chip on a tight schedule? Not one gate at a time. Simon Bloch is president and CEO of Aristo Technology Inc., Cupertino, Calif. The recent winner ...