Modern semiconductor fabrication involves aligning silicon wafers and photolithography masks to nanometre precision. As the industry shifts from using 200 mm diameter wafers to 300 mm wafers, ...

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, ...

A technique which will allow silicon wafers to be stacked accurately and inexpensively in 3-D structures has been developed by researchers at the University of Southampton. According to Dr Michael ...

An optical method for mask alignment in double-sided lithography has been developed by a team at the University of Hagen in Germany (Appl. Opt. 40 5052). The technique, which is based on the ...

Since its formation in December 2010, the SEMI 3DS-IC Standards Committee has made significant progress in establishing key standards in areas such as TSV metrology, glass carrier wafers, and ...