Yahoo Finance

Tabula Adds SystemVerilog Support to Stylus Compiler With Verific Design Automation Parser

ALAMEDA, CA--(Marketwired - Aug 13, 2013) - Verific Design Automation (www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added ...
Yahoo Finance

So-ADE Unveils Debugger for Use With Verific Design Automation's SystemVerilog, VHDL, UPF Parser Platforms

SAINT GEOIRE EN VALDAINE, FRANCE--(Marketwired - May 21, 2015) - So-ADE™ today announced immediate availability of an easy-to-use and intuitive debugger for the development and debugging of the ...
Yahoo

Verific Design Automation's Industry-Standard SystemVerilog, VHDL Parsers Linked With Aldec's Hardware Emulation Solution

ALAMEDA, CA--(Marketwire -08/15/12)- Verific Design Automation today announced it licensed its industry-standard, IEEE-compliant SystemVerilog and VHDL platform to Aldec, Inc., a global leader in ...
EDN

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
EDN

Tiempo Chooses Verific Design Automation’s SystemVerilog Front End

Tiempo, provider of breakthrough, ultra low-power asynchronous intellectual property (IP) for embedded applications, has chosen Verific Design Automation, a de facto industry standard, as the front ...
Design-Reuse

Sibridge Technologies & Axiom Design Automation Partner to Integrate Verification IPs with SystemVerilog

Santa Clara & Milpitas, California, May, 25 2011: Sibridge Technologies, a leading provider of Design and Verification IPs, with expertise in ASIC/SoC design & verification and Embedded solutions and ...
Electronic Design

First Commercial Parser Ships For System Verilog

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Linux Journal

Open Source in Electronic Design Automation

The world of open-source software is making inroads into areas beyond operating systems, Internet and desktop applications, GUIs and scripting languages. One less well-known area of open-source ...